1. Field of the Invention
The present invention relates to semiconductor integrated circuits (ICs), and, more particularly, to level shifting circuits.
2. Description of the Related Art
Most semiconductor ICs have a core circuit part for essential functions and an interfacing circuit part for interfacing with external circuits. In addition, most semiconductor ICs may include circuit blocks for various functions and power supply voltages for the respective circuit blocks may be different from each other. For example, most circuit blocks in a semiconductor IC operate with a relatively low power supply voltage under 1.3[V], whereas an analog circuit block that interfaces with external circuits typically operates with a relatively high power supply voltage of about 2.5[V]˜3.3[V].
As such, there are voltage level differences among the circuit blocks that operate with different power supply voltages, which may result in the use of level shifters as interfaces between various circuit blocks.
FIG. 1 is a circuit diagram that illustrates a conventional level shifting circuit
Referring to FIG. 1, a conventional level shifter includes N-type metal-oxide-semiconductor (NMOS) transistors MN1 and MN2 that receive differential input signals IN and INB and P-type metal-oxide-semiconductor (PMOS) transistors MP1 and MP2 that are coupled to each other in a latch configuration. The PMOS transistors MP1 and MP2 provide differential output signals OUT and OUTB at drains thereof respectively.
When the input signal IN transitions from a logic low level to a logic high level, and the input signal INB transitions from a logic high level to a logic low level, the NMOS transistor MN1 transitions from the off state to the on state and the NMOS transistor MN2 transitions from the on state to the off state. A node N2 then transitions from the logic high level to the logic low level due to a current sinking operation of the NMOS transistor MN1. During the current sinking operation of the NMOS transistor MN1, when a voltage level of the node N2 drops from a logic high level to VDDH-Vth (threshold voltage of the PMOS transistor MP2), the PMOS transistor MP2 is turned on and a node N1 transitions from the logic low level to the logic high level. Accordingly, the node N1 transitions after the node N2 transitions, which results in a delay time difference. Therefore, there is a mismatch of duty ratios of the differential output signals OUT and OUTB.
In summary, conventional level shifter circuits may generate differential output signals that have a mismatch in duty ratios due to the delay time difference of the differential output signals.